1. Field of the Invention
The present invention relates to a semiconductor substrate and a method of manufacturing a semiconductor device, and particularly to those characterized in an alignment mark for positioning a mask and a method of forming the alignment mark.
2. Description of the Related Art
A process of manufacturing a semiconductor device contains a step of transferring a pattern formed on a mask onto a semiconductor wafer. In this case, as shown in FIG. 1A, a predetermined pattern is transferred onto a chip region 2 on a semiconductor wafer 1 to form a layer which comprises the semiconductor device, and at the same time a field alignment mark (X.sub.1, Y.sub.1), for example, is transferred onto scribe areas 3X, 3Y on the semiconductor wafer 1. Such an alignment mark comprises plural basic marks M which are regularly arranged as shown in FIG. 1B. Thereafter, a pattern transfer operation is performed in a next step on the basis of the field alignment mark (X.sub.1, Y.sub.1). The alignment marks (X.sub.2, Y.sub.2), (X.sub.3, Y.sub.3), . . . for use in the respective steps are successively formed while displacing the position. This is because the respective alignment marks are prevented from being overlapped with one another and thus it is avoided that the alignment marks are identifiable.
Followed by the microstructure and multilayer structure of wires of semiconductor devices, a technique of flattening an interlayer insulating film at the lower side of a wiring layer to facilitate the processing of fine wires (microstructure wires) has been increasingly more important. However, the flattening of the interlayer insulating film makes such a disadvantage that it is difficult to see an alignment mark of a substrate for positioning a mask, particularly an alignment mark which is formed by using unevenness of the insulating film. Therefore, the alignment mark is needed to be formed in a step just before the wiring layer is formed, so that the number of alignment marks is increased and an area of the scribe region is also increased.
As a method of solving this problem, Japanese Patent Application Laid-open No. Hei-2-229419 discloses a method (prior art) of forming an alignment mark as shown in FIG. 2. This method will be hereunder described.
In a first mask step, a first pattern is formed on a chip region of a silicon substrate (wafer), and at the same time an alignment mark 4a is formed on a scribe region of the silicon substrate 1 (wafer). In a second mask step, a mask is positioned to the alignment mark 4a to form a second pattern on the chip region and at the same time an alignment mark 4b is formed.
After the second pattern is formed, a flattening layer 7 and an interlayer insulating film 5 are formed. When a third pattern forming layer 6 formed on the interlayer insulating film 5 is made of an opaque material such as aluminum or the like, an alignment mark 4c is formed on the interlayer insulating film 5 on the basis of the alignment mark 4b before the opaque film 6 is formed. The alignment mark 4c is formed at the same position as the alignment mark 4a while overlapped with the alignment mark 4a.
Before the opaque film 6 is formed, the two alignment marks 4a and 4c are detected at the same time. However, after the opaque film 6 is formed, the alignment mark 4a is unseen, and thus it does not act as an obstacle to position the mask to the alignment mark 4c. The alignment marks are formed at the same position in superposition with each other, and this arrangement reduces the occupation area of the alignment marks on the wafer.
According to the technique described in Japanese Patent Application Laid-open No. Hei-2-229419, the alignment mark 4c for use when the opaque film 6 is patterned can be formed at the same position as the alignment mark 4a. However, in this publication, no description is made on the case where an additional interlayer insulating film is further formed, a contact hole is formed therein and a wiring layer serving as an upper layer is then formed. Further, this publication makes no clear description as to whether the opaque film 6 is left on a scribe region or removed therefrom when the opaque film 6 on the chip region is patterned. When an alignment mark is formed on the scribe region by patterning the opaque film 6, it is estimated that it is formed at a position where the alignment marks 4a, 4b, 4c are not formed. Accordingly, when a semiconductor device having a multilayered wiring structure is manufactured, the reduction of the occupation area of the alignment marks on the scribe region is not sufficient.
In the above description, a pair of alignment marks are formed in a single step. However, actually, plural alignment marks are formed on the scribe regions 3X, 3Y in many cases.